Decoder and decoding method

ABSTRACT

The deterioration of an error characteristic obtained at a point where a transfer method is changed is suppressed. A first adder calculates a SM value obtained when the state 00 is changed to the state 00, and outputs it to a comparator. A second adder calculates a SM value obtained when the state 01 is changed to the state 00, and outputs it to the comparator. The comparator compares the SM values, selects a path having the larger likelihood, and outputs to a register having a set and a reset. An ACS controller detects a condition in which the state transition of fixed information TAB 1  is uniquely determined, and outputs a reset signal to the register having a set and a reset, which stores the SM value of that state, to set the value of the register to zero. The ACS controller  85  also outputs set signals to registers having sets and resets, which store the SM values of the states other than the state 00 of the fixed information TAB 1 , to set them to the maximum value.

TECHNICAL FIELD

The present invention relates to a decoding apparatus and method, andmore particularly, to a decoding apparatus and method which is capableof suppressing the decoding deterioration in transfer data when atransfer-data modulation method is changed.

BACKGROUND ART

In Japan, the Radio Regulatory Council submitted a report in whichdigital broadcasting service by the use of a broadcasting satellite(hereinafter called a BS) will be implemented by a BS4 satellite, whichwill be launched in the future. Data to be transferred includes maininformation formed of video signals and audio signals, a transfer methodindicating a data encoding rate and a modulation method, a TMCC(transmission multiplexing configuration control) signal in whichtransport stream (TS) information in data is encoded, and fixedinformation formed of special-pattern data used for stopping propagationof a transfer-data error.

The main information is encoded and transferred by a QPSK (quadraturephase shift keying) modulation method at an encoding rate R of 1/2, 2/3,3/4, 5/6, or 7/8, or at a TC8PSK (trelliscoded-coded 8 phase shiftkeying) method at an encoding rate R of 2/3. The TMCC signal and thefixed information are transferred via a BPSK (binary phase shift keying)signal encoded at an encoding rate of 1/2 (R=1/2). An encoding methodand a decoding method used when basic modulation methods (TC8PSK, BPSK,and QPSK) are employed in a time-division manner in the abovebroadcasting method will be described below by referring to FIG. 5.

An information generator 1 converts the main information, the TMCCsignal, and the fixed information, which are binary, to serial data. Aserial-to-parallel converter 2 outputs serial data as it is when theserial data is modulated by the BPSK or QPSK modulation method, andconverts serial data to two-bit parallel data and outputs it when theserial data is modulated by the TC8PSK modulation method.

An encoder 3 convolutionally encodes input data and outputs it. Amapping circuit 4 assigns input data to a BPSK, QPSK, or TC8PSK signalpoint according to the respective modulation methods, and outputs an Isignal and a Q signal to a transmission line 5.

A decoder 6 receives the I signal and the Q signal; decodes it toone-bit data when the convolutionally encoded signals have beenmodulated by the BPSK or QPSK modulation method, and decodes it totwo-bit data when the convolutionally encoded signals have beenmodulated by the TC8PSK modulation method; and outputs the data. Aparallel-to-serial converter 7 outputs an input signal as it is when theinput signal has been modulated by the BPSK or QPSK modulation method,and converts the two-bit parallel data to serial data and outputs itwhen the input signal has been modulated by the TC8PSK modulationmethod. A TMCC controller 8 controls the information generator 1 to themapping circuit 4 by the use of the TMCC signal.

The information generator 1 will be further described by referring toFIG. 6. An information output circuit 21 sends the fixed information(TAB1 and TAB2 shown in FIG. 6) to an input terminal 11-1 and an inputterminal 11-3 of a switching circuit 22, respectively; sends the TMCCsignal (TMCC shown in FIG. 6) to an input terminal 11-2; and sends themain information (main information 0 to main information 47 shown inFIG. 6) to an input terminal 12-0 to an input terminal 12-47,respectively. The switching circuit 22 switches between the inputterminals 11-1 to 11-3 and the input terminals 12-0 to 12-47 by a signalswitcher 13 in a time-division manner, generates each serial data (TAB1,TMCC, TAB2, and main information 0 to main information 47), and outputsit to the serial-to-parallel converter 2.

FIG. 7 shows a frame structure of the data switched by the signalswitcher 13 of the switching circuit 22. One superframe is formed ofeight frames, a frame 0 to a frame 7. The frame 0 is formed of the fixedinformation TAB1, TMCC, the fixed information TAB2, and the maininformation 0 to the main information 47. A frame 1 to the frame 7 areformed in the similar way to the frame 0 except that the fixedinformation TAB2 in the frame 0 is replaced with fixed information TAB3.The fixed information TAB1, the fixed information TAB2, and the fixedinformation TAB3 have special patterns of 0x1B95, 0xA340, and 0x5CBF,respectively.

As the encoder 3, a trellis encoder which performs convolutionalencoding will be described below by referring to FIG. 8. When a signalinput from the serial-to-parallel converter 2 has been modulated by amodulation method other than the TC8PSK modulation method, an input bit(one bit) is input. When the input signal has been modulated by theTC8PSK modulation method, two bits, an input bit and a parallel bit, areinput. In any of the modulation methods, the trellis encoder encodes aninput bit at an encoding rate R of 1/2 and outputs an output bit 2 andan output bit 3. The parallel bit is not encoded and output as it is asan output bit 1. In other words, the trellis encoder encodes a two-bitinput signal (input bit and parallel bit) at an encoding rate R of 2/3to generate three bits.

The input bit is input to a delay circuit 31 formed of a register, anexclusive-OR circuit 33, and an exclusive-OR circuit 34. The delaycircuit 31 delays the input input bit by a one-time-unit period, andoutputs to a delay circuit 32 and the exclusive-OR circuit 33. The delaycircuit 32 formed of a register delays the input input bit by aone-time-unit period and outputs to the exclusive-OR circuit 33 and theexclusive-OR circuit 34. The exclusive-OR circuit 33 calculates theexclusive OR of the input bit, the signal input from the delay circuit31, and the signal input from the delay circuit 32, every one-time-unitperiod, and outputs the result as the output bit 2. The exclusive-ORcircuit 34 calculates the exclusive OR of the input bit and the signalinput from the delay circuit 32, every one-time-unit period, and outputsthe result as the output bit 3.

The mapping circuit 4 maps the signal input from the encoder 3 ontosignal points shown in FIG. 9 according to the signal modulation method.FIG. 9(A) shows signal-point arrangement for the signals (fixedinformation TAB1, fixed information TAB2, and TMCC signal) modulated bythe BPSK modulation method. FIG. 9(B) shows signal-point arrangement forthe signals (main information 0 to main information 47) modulated by theTC8PSK modulation method. These signal points indicate encoded transferdata which the mapping circuit 4 outputs. Two signal points (forexample, a signal point (100) and a signal point (000)) positionedsymmetrically against the center of the circle shown in FIG. 9(B) form abranch of the encoded transfer data. In a branch, one of the signalpoints has an MSB (most significant bit) of 1 (for example, the MSB ofthe signal point (100)) and the other has an MSB of 0 (for example, theMSB of the signal point (000)), and the signal points have the same bits(for example, the lower two bits, 00, of the signal point (100) and thesignal point (000)) except the MSBs.

A Detailed structure of the decoder 6 will be described below byreferring to FIG. 10. A branch-metric (hereinafter called BM) generator41 calculates the square Euclidean distances of the received signals (I,Q) (corresponding to the I coordinate and the Q coordinate in thesignal-point arrangement shown in FIG. 9) and the signal points (forexample, the signal point (000) and the signal point (111) shown in FIG.9(B)) of each branch, respectively, and outputs as four BM signals(BM00, BM01, BM10, and BM11). The BM generator 41 also outputsparallel-bit (hereinafter called PB) information (PB00, PB01, PB10, andPB11) selected correspondingly to each branch.

When a receiving point R (−0.173, 0.984) is received as a receivedsignal modulated by the TC8PSK modulation method as shown in FIG. 11,for example, the square Euclidean distances (to say simply, the lengthsof solid lines in FIG. 11) between the receiving point R, and the signalpoints (000) and (100) are calculated, and whichever shorter (in thecase of FIG. 11, the distance between the receiving point R and thesignal point (100) since the square Euclidean distance between thereceiving point R and the signal point (100) is shorter than thatbetween the receiving point R and the signal point (000)) is set in theBM signal BM00. The MSB (=1) of the signal point (100) used in thecalculation of the BM signal BM00 is assigned to the PB information PB00corresponding to the BM signal BM00. In the same way, the squareEuclidean distances (the lengths of dotted lines in FIG. 11) between thereceiving point R, and signal points (001) and (101) are calculated. Inthis case, the distance between the receiving point R and the signalpoint (001) is set to the BM signal BM01, and a value 0 (which is theMSB of the signal point (001)) is assigned to PB information PB01. BMsignals BM10 and BM11, and PB information PB10 and PB11 are calculatedin the same way. In other words, the BM generator 41 calculates branchmetrics from the receiving point R corresponding to the received signal,and outputs BM signals and PB information used for decoding the signalpoints (transfer data) output from the mapping circuit 4.

When the receiving point R1 (−0.173, 0.984) of a signal modulated by theBPSK modulation method is received at a time t=t1 and a receiving pointR2 (−0.173, −0.984) is received at a time t=t1+1, a BM signal BM00 iscalculated by the following expression as shown in FIG. 12.

BM00=bm0(t1)+bm0(t1+1)

In this expression, bm0(t1) indicates the square Euclidean distance(=(+1−(−0.173))²) between the I component (=−0.173) of the receivingpoint R1 and the I component (=+1) of the signal point (0), andbm0(t1+1) indicates the square Euclidean distance (=(+1−(−0.173))²)between the I component (=−0.173) of the receiving point R2 and the Icomponent (=+1) of the signal point (0). A BM signal BM01 is calculatedby the following expression in the same way.

BM01=bm0(t1)+bm1(t1+1)

In this expression, bm0(t1) indicates the same value as that describedabove and therefore a description thereof is omitted, and bm1(t1+1)indicates the square Euclidean distance (=(−1−(−0.173))²) between the Icomponent (=−0.173) of the receiving point R2 and the I component (=−1)of the signal point (1). The other BM signals are calculated by thefollowing expressions in the same way.

BM10 bm1(t1)+bm0(t1+1)

BM11 bm1(t1)+bm1(t1+1)

Since a parallel bit has no meaning (since a parallel bit is not inputto the encoder 3 for a signal modulated by the BPSK modulation methodand therefore an indefinite value is output from the encoder, it has nomeaning as data) in the BPSK modulation method, any values are assignedto PB information PB00 to PB11.

FIG. 13 shows the state transitions of the basic codes (which correspondto the bits excluding the MSB of signal points used for calculating abranch metric from a receiving point, and are 00, 01, 10, and 11) of areceived signal. In other words, basic codes at a before-transitionstate and an after-transition state shown in FIG. 13 indicate theinternal states of the encoder 3 (trellis encoder). A state 00 indicatesthat the delay circuit 31 and the delay circuit 32 shown in FIG. 8 holda value 0 and a value 0, respectively, a state 01 indicates that theyhold a value 0 and a value 1, respectively, a state 10 indicates thatthey hold a value 1 and a value 0, respectively, and a state 11indicates that they hold a value 1 and a value 1, respectively. An arrowfrom each state before a transition to each state after the transitioncorresponds to a state transition. When a value 0 is input at the state00 (corresponding to the values of the delay circuit 31 and the delaycircuit 32), for-example, a value 00 (corresponding to the output bit 2and the output bit 3) is output and the state is changed to a state 00(corresponding to the values of the delay circuit 31 and the delaycircuit 32). Therefore, a symbol 0/00 shown at I/O indicates an input of0 and an output of 00. The other arrows and I/O's have the correspondingmeanings in the same way.

The above state transition can be described in the following way by theoperations of the encoder 3 shown in FIG. 8. When an input bit of 0 isinput to the encoder 3 while the register of the delay circuit 31 has avalue of 0 and the register of the delay circuit 32 has a value of 0(state 00), the encoder 3 outputs an output bit 2 of 0 and an output bit3 of 0 (output 00) as the calculation result. After the calculation, theregister of the delay circuit 31 has a value of 0 and the register ofthe delay circuit 32 has a value of 0 (transition to state 00). In thesame way, when a value of 1 is input at the state 00, a value of 11 isoutput and the state is changed to the state 10. When a value of 0 isinput at the state 10, a value of 10 is output and the state is changedto the state 01. When a value of 1 is input at the state 10, a value of01 is output and the state is changed to the state 11. The other statetransitions can be calculated in the same way.

The values (corresponding to the values (SM00, SM0, SM10, and SM11)which registers 54A to 54D having resets shown in FIG. 14 have) of thestate metrics (hereinafter called SMs) corresponding to statetransitions from each state are calculated. A sicnal output when a stateis changed correspond to a BM signal and PB information. Specifically,the output 00 corresponds to the BM signal BM00 and the PB informationPB00, the output 01 corresponds to the BM signal BM01 and the PBinformation PB01, the output 10 corresponds to the BM signal BM10 andthe PB information PB10, and the output 11 corresponds to the BM signalBM11 and the PB information PB11.

An ACS (add, compare, and select) circuit 42 receives the four pieces ofPB information (PB00, PB01, PB10, and PB11) and the four BM signals(BM00, BM01, BM10, and BM11), and outputs PB information and path memoryselection information (pb00, se100), (pb01, se101), (pb10, se110), and(pb11, se111). Details of the ACS circuit 42 will be described below byreferring to a block diagram shown in FIG. 14.

An adder 51A adds the BM signal BM00 (BM value obtained when the state00 is changed to the state 00) sent from the BM generator 41 to thevalue SM00 (the state metric value (hereinafter called SM value) at thestate 00 before the transition) of the register 54A having a reset tocalculate the likelihood (SM value) obtained when the state 00 ischanged to the state 00. An adder 52A adds the BM signal BM11 (BM valueobtained when the state 01 is changed to the state 00) sent from the BMgenerator 41 to the value SM01 (the SM value at the state 01 before thetransition) of the register 54B having a reset to calculate thelikelihood (SM value) obtained when the state 01 is changed to the state00. At the initial state of decoding, the registers 54A to 54D havingresets are reset to zero by reset signals output from a reset circuit(not shown).

After the transition, a comparator 53A compares the SM value obtainedwhen the state 00 was changed to the state 00 with the SM value obtainedwhen the state 01 was changed to the state 00, and selects whichever hasa larger-likelihood path (SM value). When the SM value (the output ofthe adder 51A) obtained when the state 00 was changed to the state 00 isequal to or smaller than that the SM value (the output of the adder 52A)obtained when the state 01 was changed to the state 00, the comparator53A outputs the smaller SM value (the output of the adder 51A) to theregister 54A having a reset, and outputs to a path memory 43 a value of0 as path-memory (hereinafter called PM) selection information se100 andPB00 corresponding to the selected SM value as the PB information pb00.Conversely, when the SM value (the output of the adder 51A) obtainedwhen the state 00 was changed to the state 00 is larger that the SMvalue (the output of the adder 52A) obtained when the state 01 waschanged to the state 00, the comparator 53A outputs the smaller SM value(the output of the adder 52A) to the register 54A having a reset, andoutputs to the path memory 43 a value of 1 as the PM selectioninformation se100 and PB11 corresponding to the selected SM value as thePB information pb00. The register 54A having a reset stores the SM valueselected by the comparator 53A as a state metric at the state 00.

An adder 51B, an adder 52B, a comparator 53B, and the register 54Bperform the same calculation as the adder 51A, the adder 52A, thecomparator 53A, and the register 54A. The SM value (path likelihood)obtained when the state 10 or the state 11 is changed to the state 01 iscalculated, and the PM selection information SE101 and the PBinformation pb01 are output to the path memory 43. As for a transitionto the state 10 and that to the state 11, the same operation isperformed. The BM generator 41 and the ACS circuit 42 perform the aboveprocessing every time a received signal (for example, the receivingpoint R shown in FIG. 11) is received.

The path memory 43 selects the maximum-likelihood path by the use ofvalues (pb00, 0), (pb01, 0), (pb10, 1), and (pb11, 1) in which values 0,0, 1, and 1 are combined with the PM selection information se100, se101,se11, and se111 and the PB information pb00, pb01, pb10, and pb11.Details of the path memory 43 will be described below by referring to ablock diagram shown in FIG. 15. The relationship between a register anda selector in each column (for example, registers 63A to 63D andselectors 64A to 64D serving as register-output destinations) in thepath memory 43 corresponds to the state transition shown in FIG. 13.Among registers in the first rows corresponding to the state 00, aregister 61A in the first column stores the value (pb00, 0)corresponding to the PB information pb00 at the state 00 sent from theACS circuit 42. A selector 62A selecting a path at the state 00 selectseither the value (pb00, 0) sent from the first-column register 61Acorresponding to the state 00 or the value (pb01, 0) sent from thefirst-column register 61B among registers in the second rowcorresponding to the state 01, according to the PM selection informationse100; outputs it to a register 63A in the second column correspondingto the state 00; and stores in it.

The first-column register 61A stores a combination of the PB informationpb00 (for example, PB00) obtained when the state is changed to the state00 and input from the ACS circuit 42, and a value 0. The first-columnregister 61B in the second row stores a combination of the PBinformation pb01 (for example, PB10) obtained when the state is changedto the state 01 and input from the ACS circuit 42, and a value 0. Thevalue of the register 61A and that of the register 61B are input to theselector 62A. The selector 62A corresponding to the state 00 outputs thevalue (pb00 (for example, the value of PB00, 0), 0) input from theregister 61A to the second-column register 63A according to the PMselection information se100 (for example, a value 0 which specifies theselection from the state 00) input from the ACS circuit 42.

In the path memory 43, selections and transitions of combined values areperformed according to the PM selection information for all columns(receiving-point count) and all states (state 00 to state 11), asdescribed above. Finally, one of the combined value (the value stored ina register 76A) of the state 00 to the combined value (the value storedin a register 76D) of the state 11 is selected according to information“smmin” indicating the minimum state-metric value as the combined valueof the maximum-likelihood state in a selector 77. The selected combinedvalue is output.

Path selection processing is applied to data input at a point of time bythe number (the number of received signals) of the columns of the pathmemory 43. This means that data input at a point of time is affected bydata input thereafter, is delayed by the number (the number of receivedsignals) of the columns of the path memory 43, and is output.

When the modulation method is changed from the BPSK method to the PC8PSKmethod at a time “t,” for example, data conforming to the BPSKmodulation method is input at a time (t−1) and a branch metric iscalculated. Then, in the ACS circuit 42, path-selection information iscalculated according to the result of the branch-metric calculation.Path-memory selection processing is performed in the path memory 43.

Until the output corresponding to the data input at the time (t−1) isobtained, however, the data of the BPSK modulation method is affected bydata which is modulated by the TC8PSK modulation method and input afterthe time “t.” Since the branch metric corresponding to data modulated bythe TC8PSK modulation method has a relatively low reliability oflikelihood than the branch metric corresponding to the data modulated bythe BPSK modulation method, the reliability of the path-selectioninformation corresponding to the data modulated by the TC8PSK modulationmethod is also lower. As a result, although transfer is performed by theBPSK modulation method to increase reliability, since the transfermethod is changed to the TC8PSK modulation method, an errorcharacteristic deteriorates at a point where the transfer method ischanged.

DISCLOSURE OF THE INVENTION

The present invention has been made in consideration of the abovesituation. Accordingly, it is an object of the present invention todetect the position of fixed information in transferred dataconvolutionally encoded, to determine whether a code transition state isterminated, and to control the value of a state metric, such that thedeterioration of an error characteristic in decoding the transfer datais suppressed when the transfer-data modulation method is changed.

In order to solve the above problem, in the present invention, adecoding apparatus for decoding transfer data in which main informationand fixed information are convolutionally encoded includes: a generationmeans for generating the branch metric corresponding to the transitionstate of the code of the convolutionally encoded transfer data; aselection means for calculating a state metric according to the branchmetric and for selecting the path of the code; a detection means fordetecting the position of the fixed information in the transfer data; acontrol means for controlling the value of the state metric of the fixedinformation correspondingly to a detection result obtained by thedetection means; and a storage means for storing the selection state ofthe path of the code according to the selection of the path.

Further, a decoding method for decoding transfer data in which maininformation and fixed information are convolutionally encoded includes:a generation step of generating the branch metric corresponding to thetransition state of the code of the convolutionally encoded transferdata; a selection step of calculating a state metric according to thebranch metric and of selecting the path of the code; a detection step ofdetecting the position of the fixed information in the transfer data; acontrol step of controlling the value of the state metric of the fixedinformation correspondingly to a detection result obtained in thedetection step; and a storage step of storing the selection state of thepath of the code according to the selection of the path.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a trellis diagram indicating the state transition of fixedinformation TAB1.

FIG. 2 is a block diagram showing an example structure of an ACS circuit42 to which the present invention is applied.

FIG. 3 is a view illustrating an example of timing when the ACS circuit42 shown in FIG. 2 executes termination processing.

FIG. 4 is a block diagram showing another example structure of anencoder 3.

FIG. 5 is a block diagram showing a transfer system in which a signal isencoded, transferred, and decoded.

FIG. 6 is a block diagram showing details of a structure of aninformation generator 1 shown in FIG. 5.

FIG. 7 is a view showing the frame state of a signal output from aswitching circuit 22 shown in FIG. 6.

FIG. 8 is a block diagram showing a detailed structure of the encoder 3shown in FIG. 5.

FIG. 9 is a view showing signal points on which signals are mapped in amapping circuit 4 shown in FIG. 5.

FIG. 10 is a block diagram showing a detailed structure of a decoder 6shown in FIG. 5.

FIG. 11 is a view showing a branch metric obtained when a BM generator41 shown in FIG. 10 generates a BM signal.

FIG. 12 is a view showing a branch metric obtained when a BM generator41 shown in FIG. 10 generates a BM signal.

FIG. 13 is a view showing the transition states of signals in theencoder 3 shown in FIG. 5.

FIG. 14 is a block diagram showing a detailed structure of an ACScircuit 42 shown in FIG. 10.

FIG. 15 is a block diagram showing a detailed structure of a path memory43 shown in FIG. 10.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention will be described below. Since the fundamentalstructure of a system formed of an encoding apparatus and a decodingapparatus according to the present invention is the same as in a caseshown in FIG. 5, the corresponding symbols are used in the followingdescription.

In the superframe 1 shown in FIG. 7, since the fixed information TAB1and the fixed information TAB2 are 16-bit signals having the specialpatterns specified in advance, when the first two bits of each fixedinformation are input to the encoder 3 shown in FIG. 8, the internalstate of the encoder 3 is uniquely determined. Specifically, until thefirst two bits of the fixed information TAB1 are input, for example,since the output of the encoder 3 is determined by the data of maininformation 47 in a frame 7 of the superframe 0, which is a signalhaving no special pattern and stored in the delay circuit 32, the outputis not uniquely determined. When the remaining 16 bits, starting withthe third bit, are continuously input, the output of the encoder 3 isuniquely determined. In the present invention, such a condition isregarded as the termination of convolutional codes (trellis codes), andthe decoder performs the corresponding processing (hereinafter calledtermination processing) to suppress the deterioration of an errorcharacteristic at a point where the transfer method is changed.

FIG. 1 is a trellis diagram indicating the state transitions of basiccodes, obtained when the fixed information TAB1 is input to the decoder6. It is assumed that a time t=0 corresponds to timing when the firstbit of the fixed information TAB1 is input to the encoder 3. The stateof the encoder 3 at that time is determined by the information bit (thelast bit of the data of the main information 47 in the frame 7 of thesuperframe 0) immediately before the fixed information TAB1 and thefirst bit of the fixed information TAB1. Since the information bitimmediately before the fixed information TAB1 can be any value, it isnot determined whether the state of the encoder 3 is the state 00 or thestate 01. At timing when the second bit of the data (0x1B95=“0001 10111001 0101”) of the fixed information TAB1 is input at a time t=1, thestate of the fixed information is uniquely determined to be the state00. The state is uniquely changed whenever a bit of the data of thefixed information TAB1 is input as shown in FIG. 1.

The decoder 6 determines that the convolutional codes of the fixedinformation is terminated when the state of the input fixed informationis uniquely determined, and performs the termination processingcorresponding thereto.

To perform the termination processing, an ACS circuit 42 according tothe present invention is configured as shown in FIG. 2. In a decoder 6,a BM generator 41 and a path memory 43 can have the same structures asthose in the conventional case. In the ACS circuit 42 shown in FIG. 2,since an adder 81A, an adder 82A, and a comparator 83A have the samestructures as the adder 51A, the adder 52A, and the comparator 53A inthe ACS circuit 42 shown in FIG. 14, descriptions thereof will beomitted.

A register 84A having a set and a reset stores the SM value of the state00, selected by the comparator 83A. A register 84B having a set and areset stores the SM value of the state 01, selected by the comparator83B. A register 84C having a set and a reset stores the SM value of thestate 10, selected by the comparator 83C. A register 84D having a setand a reset stores the SM value of the state 11, selected by thecomparator 83D. An ACS controller 85 outputs signals for controlling thevalues of the registers 84A to 84D having sets and resets.

The operation of the ACS circuit 42 will be described next. At theinitial state of decoding, the ACS controller 85 outputs reset signalsto the registers 84A to 84D having sets and resets to set the values ofthe registers to zero. When a signal SFST indicating the position of thetop of a superframe is input, the ACS controller 85 understands theposition of the superframe, and with the position thereof being used asthe reference, the positions of the fixed information TAB1 and the fixedinformation TAB2.

When data (second bit) of the fixed information TAB1 is input to theencoder 3 at the time t=1 shown in FIG. 1, for example, since theinternal state of the encoder 3 is set to the state 00, if thecorresponding data (BM signal and PB information at the time t=1) isinput to the ACS circuit 42, the ACS controller 85 performs thetermination processing.

In a circuit ACS00 which corresponds to the state 00 of the ACS circuit42 at the time t=1, the adder 81A adds the BM signal BM00 (BM valueobtained when the state 00 is changed to the state 00) sent from the BMgenerator 41 to the value (which has been set to zero by the ACScontroller 85) of the register 84A having a reset (to calculate the SMvalue obtained when the state 00 is changed to the state 00 at the timet=1), and outputs it to the comparator 83A. The adder 82A adds the BMsignal BM11 (BM value obtained when the state 01 is changed to the state00) sent from the BM generator 41 to the value (which has been set tozero by the ACS controller 85) of the register 84B having a reset (tocalculate the SM value obtained when the state 01 is changed to thestate 00 at the time t=1), and outputs it to the comparator 83A.

The comparator 83A compares the SM value obtained when the state 00 waschanged to the state 00 with the SM value obtained when the state 01 waschanged to the state 00, and selects whichever has a larger-likelihoodpath (SM value). More specifically, when the SM value (the output of theadder 81A) obtained when the state 00 was changed to the state 00 isequal to or smaller that the SM value (the output of the adder 82A)obtained when the state 01 was changed to the state 00, the comparator83A outputs the smaller SM value (the output of the adder 81A) to theregister 84A having a reset, and outputs to a path memory 43 a value of0 as the PM selection information se100 and PB00 corresponding to theselected SM value as the PB information pb00.

Conversely, when the SM value (the output of the adder 81A) obtainedwhen the state 00 was changed to the state 00 is larger that the SMvalue (the output of the adder 82A) obtained when the state 01 waschanged to the state 00, the comparator 83A outputs the smaller SM value(the output of the adder 82A) to the register 84A having a reset, andoutputs to the path memory 43 a value of 1 as the PM selectioninformation se100 and PB11 corresponding to the selected SM value as thePB information pb00. A circuit ACS01 which performs calculation when thestate is changed to the state 01 of the ACS circuit 42, a circuit ACS10which performs calculation (calculation of an SM value, generation of PMselection information, and selection of PB information) when the stateis changed to the state 10, and a circuit ACS11 which performscalculation (calculation of an SM value, generation of PM selectioninformation, and selection of PB information) when the state is changedto the state 11 execute the same calculation as the circuit ACS00.

The circuit ACS00 of the ACS circuit 42 executes calculation for thestate 00, which is a uniquely determined state of the fixed informationTAB1 at the time t=1. In this case, the ACS controller 85 outputs areset signal to the register 84A having a set and a reset to set thevalue of the register to zero. In other words, the SM value calculatedat the time t=1 in the state 00 is changed to the value 0. This SM valueis to be used as the value of the register 84A having a set and a resetin the state 00 at a time t=2.

The circuit ACS01, which performs calculation (calculation of an SMvalue, generation of PM selection information, and selection of PBinformation) when the state is changed to the state 01 of the ACScircuit 42, has not executed calculation (at the time t=1, the state wasnot changed to the state 01) for the state 00, which is a uniquelydetermined state of the fixed information TAB1 at the time t=1. The ACScontroller 85 outputs a set signal to the register 84B having a set anda reset which stores the SM value of the state 01 to set the value ofthe register to the maximum value. In other words, in the circuit ACS01in the state 01, the SM value (the value of the register 84B having aset and a reset) calculated at the time t=1 is changed to the maximumvalue. This SM value is to be used as the value of the register 84Bhaving a set and a reset in the state 01 at the time t=2. The ACScontroller 85 applies the same processing (for setting the values of theregisters 84C and 84D having sets and resets to the maximum value) asthat for the circuit ACS01, to the circuit ACS10, which performscalculation (calculation of an SM value, generation of PM selectioninformation, and selection of PB information) when the state is changedto the state 10 at the time t=1, and the circuit ACS11, which performscalculation (calculation of an SM value, generation of PM selectioninformation, and selection of PB information) when the state is changedto the state 11.

As described above, in the termination processing, the value of theregister having a set and a reset which has calculated the SM value ofthe uniquely determined state is changed to zero, and the values of theregisters having sets and resets which have calculated the SM values ofother states are changed to the maximum value. These changed values ofthe registers having sets and resets are used when the next data isinput, and make the SM value of a selected path the minimum and the SMvalues of not-selected paths the maximum. Therefore, it is advantageousthat, with a comparison of SM values, a path selection state becomesclear.

It is desirable that the maximum value of the state metric be largerthan twice the maximum value (constraint length K (=3)−1=2) of thebranch metric. With a trade-off between a hardware structure and theamount of deterioration in an error-correcting capability being takeninto account, the maximum value may be not necessarily larger than themaximum value of the branch metric.

In the same way, at the time t=2, since the internal state of theencoder 3 becomes the state 00, the ACS controller 85 sets the SM valueSM00 (the value of the register 84A having a set and a reset) of thestate 00 to zero; and the SM value SM01 (the value of the register 84Bhaving a set and a reset) of the state 01, the SM value SM10 (the valueof the register 84C having a set and a reset) of the state 10, and theSM value SM11 (the value of the register 84D having a set and a reset)of the state 11 to the maximum value. At a time t=3, since the internalstate of the encoder 3 becomes the state 10, the SM value SM10 of thestate 10 is set to zero; and the SM value SM00 of the state 00, the SMvalue SM01 of the state 01, and the SM value SM11 of the state 11 areset to the maximum value.

The above termination processing is executed until the value 1 (thevalue of the last bit of the special-pattern value 1B95 of the fixedinformation TAB1 shown in FIG. 1) of the last bit of the fixedinformation TAB1, which corresponds to a time t=15, is input. Since asignal received at a time t=16 is a TMCC signal, the terminationprocessing is not performed but the same ACS processing as for theconventional ACS circuit 42 (the ACS circuit 42 shown in FIG. 13) isperformed.

Since the fixed information TAB2 is fixed data (of 0xA340=“1010 00110100 0000”), the above termination processing is executed according tothe uniquely determined state transition in the same way as for thefixed information TAB1, from processing for the received signalcorresponding to the second bit of the data of the fixed informationTAB2 to processing for the received signal corresponding to the 16th bitof the data of the fixed information TAB2. The same processing as forthe conventional ACS circuit 42 is applied to data positioned after thedata of the fixed information TAB2 because it is the data of the maininformation 0.

The above-described ACS circuit 42 applies the termination processing toall of the data of the fixed information TAB1 and the fixed informationTAB2. The same advantage is obtained if the termination processing isapplied to a part of the data of the fixed information.

With the fixed information TAB1 being taken as an example, the state ofthe fixed information TAB1 is uniquely determined to be the state 00only when the first bit of the data of the fixed information TAB1 isinput at the time t=0 and then the second bit of the data of the fixedinformation TAB1 is input at the time t=1 in FIG. 1. The ACS circuit 42does not perform the termination processing at the time t=1 but executesit at the time t=15 (when the 16th bit of the data of the fixedinformation TAB1 is input). Since the state is changed to the state 10(as shown in FIG. 8, a new bit in the LSB side is indicated at the left)at the time t=15, the ACS controller 85 sets the SM value SM10 of thestate 10 to zero, and the SM value SM00 of the state 00, the SM valueSM01 of the state 01, and the SM value SM11 of the state 11 to themaximum value (the same as the above-described maximum value). The ACScircuit 42 executes the same processing (the termination processing isnot performed) as the conventional ACS circuit 42 at the time t=16 sincea TMCC signal is input. In other words, the termination processing isexecuted immediately before the type of the signal is changed, andthereby, the same advantage as that obtained when the terminationprocessing is applied to all data is obtained.

As for the fixed information TAB2, the above-described advantage isobtained if the termination processing is executed immediately after thetype of the signal is changed, namely, only when the second bit of thefixed information TAB2 is input. When the first bit of the fixedinformation TAB2 is input, since the state is not uniquely determined,it is not appropriate that the termination processing is executed atthat timing.

As an ACS circuit for executing the termination processing when the typeof the signal is changed, the ACS circuit 42 can be used as it is. TheACS controller 85 outputs a reset signal to an appropriate registerhaving a set and a reset (in the termination processing for the data ofthe fixed information TAB1, for example, the register 84C having a setand a reset corresponding to the state 10 at the time t=15) only whenthe timing for the termination processing is detected by the SFSTsignal, and outputs set signals to appropriate registers having sets andresets (in the termination processing for the data of the fixedinformation TAB1, for example, the registers 84A, 84B, and 84C havingsets and resets, at the time t=15).

FIG. 3 indicates timing when the ACS controller 85 outputs set signalsand reset signals to registers having sets and resets. When the 16th bitof the fixed information TAB1 is input at the time t=15, the ACScontroller 85 outputs a reset signal to the register 84C having a setand a reset, which stores the SM value SM10 of the state 10 at thattime, and outputs set signals to registers having sets and resets, whichstore the state metric values of the other states, the register 84A(which stores the SM value SM00), the register 84B (which stores the SMvalue SM 01), and the register 84D (which stores the SM value SM 11).When the second bit of the fixed information TAB2 is input, the ACScontroller 85 outputs a reset signal to the register 84B having a setand a reset, which stores the SM value SM01 of the state 01 at thattime, and outputs set signals to registers having sets and resets, whichstore the state metric values of the other states, the register 84A(which stores the SM value SM00), the register 84C (which stores the SMvalue SM 10), and the register 84D (which stores the SM value SM 11).

In the BS broadcasting system, if the termination processing is executedwhen the type of the signal is changed (for example, the signal ischanged from the fixed information TAB1 to the TMCC signal, or from theTMCC signal to the fixed information TAB), since the TMCC signal usedfor informing the transfer method is not affected by the previous andfollowing signals (fixed information TAB1 and TAB2) which have adifferent signal type, an error characteristic is improved.

Within the period (time t=1 to time t=15 in FIG. 1) in which the statetransition is uniquely determined against the input of fixedinformation, with a trade-off between the error correcting capabilityand processing resource of the decoder 6 being taken into account, thetiming and the frequency of the termination processing can be thoseother than those described before. For example, the terminationprocessing can be executed only when the seventh bits of the fixedinformation TAB1 and the fixed information TAB2 are input. Since bothstates of the fixed information TAB1 and TAB2 are the state 10 at thistiming, the ACS controller 85 can use the same output timing of setsignals and reset signals and the same maximum value for both fixedinformation TAB1 and fixed information TAB2. Therefore, the circuitstructure can be simplified. The timing is not limited to that when theseventh bits of the fixed information TAB1 and TAB2 are input, and maybe that when both have the same state.

The termination processing does not necessarily need to be executed forboth fixed information TAB1 and fixed information TAB2. The terminationprocessing may be executed for either timing (when the signal ischanged, for example, timing when the last bit of the fixed informationTAB1 is input or timing when the second bit of the fixed informationTAB2 is input).

The encoder (trellis encoder) 3 shown in FIG. 8 has been simplified forthe convenience of the description. FIG. 4 shows a structure of anencoder (trellis encoder) 3 actually employed by the Japanese BS digitalbroadcasting method. In this trellis encoder, in the same way as in theencoder 3 shown in FIG. 8, an input bit and a parallel bit are input,the input bit is encoded at an encoding rate R of 1/2, the parallel bitis not encoded but output as it is, and the encoding rate R of theentire encoder is 2/3.

Since the trellis encoder has a constraint length K of 7 in encoding aninput bit, six delay circuits (a delay circuit 91 to a delay circuit 96)formed of registers are provided. Each of the delay circuit 91 to thedelay circuit 96 delays an input bit by a one-time-unit period andoutputs it. An exclusive-OR circuit 97 calculates the exclusive OR ofthe input bit, the output signal of the delay circuit 91, the outputsignal of the delay circuit 92, the output signal of the delay circuit93, and the output signal of the delay circuit 96, and outputs an outputbit 2. An exclusive-OR circuit 98 calculates the exclusive OR of theinput bit, the output signal of the delay circuit 92, the output signalof the delay circuit 93, the output signal of the delay circuit 95, andthe output signal of the delay circuit 96, and outputs an output bit 3.

Since this trellis encoder has a constraint length K of 7, 64 (=2⁷)internal states exist. When the sixth bit of input data is stored (whenthe seventh bit is input), the state-transition state of fixedinformation is uniquely determined. A decoder corresponding to thistrellis encoder can be structured by extending the number of theinternal states to 64. The operation of the decoder is also the same,the description of the decoder will be omitted.

In the present specification, information providing media for providingthe user with a computer program which executes the above processinginclude transfer media, such as Internet and digital satellites, inaddition to information recording media, such as magnetic disks andCD-ROMs.

According to the decoding apparatus as described above, the position ofthe fixed information in the convolutionally encoded transfer data isdetected, and the state-metric value of the fixed information iscontrolled when the transition state of the code of the fixedinformation is terminated. Therefore, the deterioration of an errorcharacteristic in decoding obtained when the transfer-data modulationmethod is changed is suppressed with a very simple circuit structure,and the circuit is made compact and needs less power.

Industrial Applicability

The present invention is utilized for a digital broadcasting system, forexample, a digital broadcasting service using a broadcasting satellite.

What is claimed is:
 1. A decoding apparatus for decoding transfer datain which main information and fixed information are convolutionallyencoded, comprising: generation means for generating a branch metriccorresponding to a transition state of a code of the convolutionallyencoded transfer data; selection means for calculating a state metricaccording to said branch metric and for selecting a path for said code;detection means for detecting a position of said fixed information insaid transfer data; control means for controlling a value of said statemetric of said fixed information corresponding to a detection resultobtained by said detection means; and storage means for storing aselection state of said path of said code based on the selection of thepath.
 2. The decoding apparatus according to claim 1, wherein saidcontrol means controls values of state metrics of all of the fixedinformation after a transition of the code of the fixed information isterminated.
 3. The decoding apparatus according to claim 1, wherein saidcontrol means controls the value of the state metric of the fixedinformation positioned at an arbitrary location after a transition ofthe code of the fixed information is terminated.
 4. The decodingapparatus according to claim 1, wherein said control means controlsvalues of state metrics of the fixed information positioned at aplurality of locations after a transition of the code of the fixedinformation is terminated.
 5. The decoding apparatus according to claim1, wherein when states of codes of a plurality of the fixed informationobtained after a transition of the codes of the plurality of the fixedinformation is terminated are the same, said control means controls thevalue of the state metric at one location corresponding to each of theplurality of the fixed information.
 6. A decoding method for a decodingapparatus which decodes transfer data in which main information andfixed information are convolutionally encoded, comprising the steps of:generating a branch metric corresponding to a transition state of a codeof the convolutionally encoded transfer data; calculating a state metricaccording to said branch metric selecting a path for said code;detecting a position of said fixed information in the transfer data;controlling a value of said state metric of said fixed informationcorresponding to a detection result obtained in said detection step; andstoring the selection state of said path of said code based on theselection of the path.
 7. The decoding method according to claim 6,wherein said control step controls values of state metrics of all thefixed information after a transition of the codes of the fixedinformation is terminated.
 8. The decoding method according to claim 6,wherein said control step controls the value of the state metric of thefixed information positioned at an arbitrary location after a transitionof the code of the fixed information is terminated.
 9. The decodingmethod according to claim 6, wherein said control step controls valuesof state metrics of the fixed information positioned at a plurality ofarbitrary locations after a transition of the code of the fixedinformation is terminated.
 10. The decoding method according to claim 6,wherein when states of codes of a plurality of the fixed informationobtained after a transition of codes of the plurality of the fixedinformation is terminated are the same, said control step controls thevalue of the state metric at one location corresponding to each of theplurality of the fixed information.